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? semiconductor components industries, llc, 2013 march, 2013 ? rev. 1 1 publication order number: ncp4304/d NCP4304A, ncp4304b secondary side synchronous rectification driver for high efficiency smps topologies the NCP4304A/b is a full featured controller and driver tailored to control synchronous rectification circuitry in switch mode power supplies. due to its versatility, it can be used in various topologies such as flyback, forward and half bridge resonant llc. the combination of externally adjustable minimum on and off times helps to fight the ringing induced by the pcb layout and other parasitic elements. therefore, a reliable and noise less operation of the sr system is insured. the extremely low turn off delay time, high sink current capability of the driver and automatic package parasitic inductance compensation system allow to maximize synchronous rectification mosfet conduction time that enables further increase of smps efficiency. finally, a wide operating v cc range combined with two versions of driver voltage clamp eases implementation of the sr system in 24 v output applications. features ? self-contained control of synchronous rectifier in ccm, dcm, and qr flyback applications ? precise true secondary zero current detection with adjustable threshold ? automatic parasitic inductance compensation input ? typically 40 ns turn off delay from current sense input to driver ? zero current detection pin capability up to 200 v ? optional ultrafast trigger interface for further improved performance in applications that work in deep ccm ? disable input to enter standby or low consumption mode ? adjustable minimum on time independent of v cc level ? adjustable minimum off time independent of v cc level ? 5 a/2.5 a peak current sink/source drive capability ? operating voltage range up to 30 v ? gate drive clamp of either 12 v (NCP4304A) or 6 v (ncp4304b) ? low startup and standby current consumption ? maximum frequency of operation up to 500 khz ? soic ? 8 package ? these are pb-free devices typical applications ? notebook adapters ? high power density ac/dc power supplies ? gaming consoles ? all smps with high efficiency requirements device package shipping ? ordering information NCP4304Adr2g soic ? 8 (pb ? free) 2500 / tape & reel soic ? 8 d suffix case 751 marking diagram 4304x = specific device code x = a or b a = assembly location l = wafer lot y = year w = work week = pb ? free package http://onsemi.com 1 8 4304x alyw 1 8 ncp4304bdr2g soic ? 8 (pb ? free) 2500 / tape & reel 2 3 4 1 7 6 5 8 trig/disable min_toff v cc min_ton drv gnd comp cs ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. pinout information (*note: microdot may be in either location) ncp 4304x alyw 1 dfn8 case 488af NCP4304Amntwg dfn8 (pb ? free) 4000 / tape & reel ncp4304bmntwg dfn8 (pb ? free) 4000 / tape & reel (note: for dfn the exposed pad must be either unconnected or preferably connected to ground. the gnd pin must be always connected to ground.)
NCP4304A, ncp4304b http://onsemi.com 2 figure 1. typical application example ? llc converter figure 2. typical application example ? dcm or qr flyback converter vbulk flyback control circuitry +vout gnd ok1 r1 r2 r5 r3 r4 c1 c2 c3 c4 c5 d3 d4 d5 tr1 m1 m2 r6 + + + vcc drv fb cs
NCP4304A, ncp4304b http://onsemi.com 3 pin function description pin no. pin name function pin description 1 v cc supplies the driver v cc supply terminal of the controller. accepts up to 30 v continuously. 2 min_toff minimum off time adjust adjust the minimum off time period by connecting resistor to ground. 3 min_ton minimum on time adjust adjust the minimum on time period by connecting resistor to ground. 4 trig/disable forced reset input this ultrafast input turns off the sr mosfet in ccm applications. activates sleep mode if pulled up for more than 100 s. 5 cs current sense of the sr mosfet this pin detects if the current flows through the sr mosfet and/or its body diode. basic turn off detection threshold is 0 mv. a resistor in series with this pin can modify the turn off threshold if needed. 6 comp compensation inductance connection use as a kelvin connection to auxiliary compensation inductance. if sr mos- fet package parasitic inductance compensation is not used (like for smt mosfets), connect this pin directly to gnd pin. 7 gnd ic ground ground connection for the sr mosfet driver and v cc decoupling capacitor. ground connection for minimum ton, toff adjust resistors and trigger input. gnd pin should be wired directly to the sr mosfet source terminal/solder- ing point using kelvin connection. 8 drv gate driver output driver output for the sr mosfet. figure 3. internal circuit architecture minimum off time generator min_t off detection cs & compensation cs minimum on time generator min_t on comp 1k5 trig/disable & & zcd set zcd reset enable set blanking of cs during enable reset s r q q timer drv reset drv set enable drv v cc gnd v cc management uvlo sleep mode drv out driver s r q q & inv inv or or one shoot zcd reset v dd v dd v dd v th = 2 v v dd & one shoot 150 ns inv trigger blanking 150 ns during drv rising edge generator min t off start generator min t on start 100 s min t off , min t on 100 a 10 a
NCP4304A, ncp4304b http://onsemi.com 4 maximum ratings symbol rating value unit v cc ic supply voltage ? 0.3 to 30 v v drv driver output voltage ? 0.3 to 17 v v cs current sense input dc voltage ? 4 to 200 v v csdyn current sense input dynamic voltage (t pw = 200 ns) ? 10 to 200 v v trig trigger input voltage ? 0.3 to 10 v v min_ton , v min_toff min_ton and min_toff input voltage ? 0.3 to 10 v i _min_toff , i _min_toff min_ton and min_toff current ? 10 to +10 ma vgnd ? comp static voltage difference between gnd and comp pins (internally clamped) ? 3 to 10 v vgnd ? comp_dyn dynamic voltage difference between gnd and comp pins (t pw = 200 ns) ? 10 to 10 v icomp current into comp pin ? 5 to 5 ma r ja thermal resistance junction ? to ? air, soic ? a/b versions 180 c/w r ja thermal resistance junction ? to ? air, dfn ? a/b versions, 50 mm 2 ? 1.0 oz. copper spreader 180 c/w r ja thermal resistance junction ? to ? air, dfn ? a/b versions, 600 mm 2 ? 1.0 oz. copper spreader 80 c/w t jmax maximum junction temperature 160 c t smax storage temperature range ? 60 to +150 c t lmax lead temperature (soldering, 10 s) 300 c esd capability, human body model except pin v cs ? pin 5, hbm esd capability on pin 5 is 650 v 2 kv esd capability, machine model 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: pin 1 ? 8: human body model 2000 v per jedec standard jesd22 ? a114e. machine model method 200 v pre jedec standard jesd22 ? a115 ? a 2. this device meets latchup tests defined by jedec standard jesd78. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v, c load = 0 nf, r _min_ton = r _min_toff = 10 k , v trig = 0 v, f_cs = 100 khz, dc_cs = 50%, v cs_high = 4 v, v cs_low = ? 1 v unless otherwise noted) symbol rating pin min typ max unit supply section v cc_on turn ? on threshold level (v cc going up) 1 9.3 9.9 10.5 v v cc_off minimum operating voltage after turn ? on (v cc going down) 1 8 . 3 8.9 9.5 v v cc_hyste v cc hysteresis 1 0.6 1. 0 1.4 v i cc1 _ a i cc1 _ b internal ic consumption (no output load on pin 8, f sw = 500 khz, t on_min = 500 ns, t off_min = 620 ns) 1 ? ? 4.5 4.0 6.6 6.2 ma i cc2_a i cc2_b internal ic consumption (c load = 1 nf on pin 8, f sw = 400 khz, t on_min = 500 ns, t off_min = 620 ns) 1 ? ? 9.0 6.5 12 9 ma i cc3_a i cc3_b internal ic consumption (c load = 10 nf on pin 8, f sw = 400 khz, t on_min = 500 ns, t off_min = 620 ns) 1 ? ? 57 .0 35.0 80 65 ma i cc_startup startup current consumption (v cc = v cc_on ? 0.1 v, no switching at cs pin) 1 ? 35 75 a i cc_disable_1 current consumption during disable mode (no switching at cs pin, v trig = 5 v) 1 ? 45 90 a i cc_disable_2 current consumption during disable mode (cs pin is switching, f sw = 500 khz, v cs_high = 4 v, v cs_low = ? 1 v, v trig = 5 v) 1 ? 200 330 a 3. guaranteed by design.
NCP4304A, ncp4304b http://onsemi.com 5 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v, c load = 0 nf, r _min_ton = r _min_toff = 10 k , v trig = 0 v, f_cs = 100 khz, dc_cs = 50%, v cs_high = 4 v, v cs_low = ? 1 v unless otherwise noted) symbol unit max typ min pin rating drive output t r_a output voltage rise ? time for a version (c load = 10 nf) 8 ? 120 ? ns t r_b output voltage rise ? time for b version (c load = 10 nf) 8 ? 80 ? ns t f_a output voltage fall ? time for a version (c load = 10 nf) 8 ? 50 ? ns t f_b output voltage fall ? time for b version (c load = 10 nf) 8 ? 35 ? ns r oh driver source resistance (note 3) 8 ? 1.8 7 r ol driver sink resistance 8 ? 1 2 i drv_pk(source) output source peak current 8 ? 2.5 ? a i drv_pk(sink) output sink peak current 8 ? 5 ? a v drv(min_a) minimum drive output voltage for a version (v cc = v ccoff + 200 mv) 8 8.3 ? ? v v drv(min_b) minimum drive output voltage for b version (v cc = v ccoff + 200 mv) 8 4.5 ? ? v v drv(clmp_a) driver clamp voltage for a version (12 < v cc < 28, c load = 1 nf) 8 10 12 14.3 v v drv(clmp_b) driver clamp voltage for b version (12 < v cc < 28, c load = 1 nf) 8 5 6 8 v cs input t pd_on the total propagation delay from cs input to drv output turn on (vcs goes down from 4 v to ? 1 v, t f_cs = 5 ns, comp pin connected to gnd) 5, 8 ? 60 9 0 ns t pd_off the total propagation delay from cs input to drv output turn off (vcs goes up from ? 1 v to 4 v, t r_cs = 5 ns, comp pin connected to gnd), (note 3) 5, 8 ? 4 0 55 ns i shift_cs current sense input current source (v cs = 0 v) 5 95 100 105 a v th_cs_on current sense pin turn ? on input threshold voltage 5, 8 ? 120 ? 85 ? 50 mv v th_cs_off current sense pin turn ? off threshold voltage, comp pin connected to gnd (note 3) 5, 8 ? 1 ? 0 mv g comp compensation inverter gain 5,6,8 ? 1 ? i cs _ leakage current sense input leakage current, v cs = 200 vdc 5 ? ? 1 a trigger/disable input t trig_pw_min minimum trigger pulse width (note 3) 4 3 0 ? ? ns v trig trigger input threshold voltage (v trig goes up) 4 1.5 ? 2.5 v t p_trig propagation delay from trigger input to the drv output (v trig goes up from 0 to 5 v , t r_trig = 5 ns) 4 ? 13 3 0 ns t trig_light_load light load turn off filter duration 4 70 100 130 s t trig_light_load_rec. ic operation recovery time when leaving light load disable mode (v trig goes down from 5 to 0 v , t f_trig = 5 ns) 4 ? ? 10 us t t_blank blanking time of trigger/dis during drv rising edge (v cs < v th_cs_on , single pulse on trigger/dis t trig_pw = 50 ns) 4 ? 12 0 ? ns i trig trigger input pull down current (v trig = 5 v) 4 ? 10 ? a minimum t on and t off adjust t on_min minimum t on period (r t_on_min = 0 ) 3 ? 130 ? ns t off_min minimum t off period (r t_off_min = 0 ) 2 560 6 00 690 ns t on_min minimum t on period (r t_on_min = 10 k ) 3 0.9 1 .0 1.1 s t off_min minimum t off period (r t_off_min = 10 k ) 2 0.9 1 .0 1.1 s t on_min minimum t on period (r t_on_min = 50 k ) 3 ? 4.8 ? s t off_min minimum t off period (r t_off_min = 50 k ) 2 ? 4.8 ? s 3. guaranteed by design.
NCP4304A, ncp4304b http://onsemi.com 6 typical characteristics 9.820 9.830 9.840 9.850 9.860 9.870 9.880 9.890 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 figure 4. v cc startup voltage temperature ( c) v ccon (v) 8.790 8.800 8.810 8.820 8.830 8.840 8.850 8.860 8.870 8.880 ? 40 ? 25 ? 105 203550658095110125 figure 5. v cc turn ? off voltage temperature ( c) v ccoff (v) 1.000 1.005 1.010 1.015 1.020 1.025 1.030 1.035 1.040 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 figure 6. v cc hysteresis temperature ( c) v cc_hyste (v) figure 7. startup current temperature ( c) i cc_startup ( a) 11.0 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 12.0 ? 40 ? 25 ? 105 203550658095110125 figure 8. driver high level ? a version, v cc = 12 v and c load = 1 nf temperature ( c) v drv(h)_a (v) @ v cc = 12 v and c load 1 nf 12.025 12.030 12.035 12.040 12.045 12.050 12.055 12.060 12.065 ? 40 ? 25 ? 105 203550658095110125 v drv(h)_a (v) @ v cc = 12 v and c load 10 nf figure 9. driver high level ? a version, v cc = 12 v and c load = 10 nf temperature ( c) 30 32 34 36 38 40 42 44 ? 40 ? 25 ? 105 203550658095110125
NCP4304A, ncp4304b http://onsemi.com 7 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 figure 10. driver high level ? b version, v cc = 12 v and c load = 1 nf temperature ( c) v drv(h)_b (v) @ v cc = 12 v and c load 1 nf 7.20 7.25 7.30 7.35 7.40 7.45 7.50 7.55 7.60 7.65 7.70 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 v drv(h)_b (v) @ v cc = 12 v and c load 10 nf figure 11. driver high level ? b version, v cc = 12 v and c load = 10 nf temperature ( c) 8.75 8.80 8.85 8.90 8.95 9.00 9.05 9.10 ? 40 ? 25 ? 105 203550658095110125 v drv(min_a) (v) figure 12. minimal driver high level ? a version, v cc_off + 0.2 v and c load = 0 nf temperature ( c) 5.80 5.90 6.00 6.10 6.20 6.30 6.40 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 v drv(min_b) (v) figure 13. minimal driver high level ? b version, v cc_off + 0.2 v and c load = 0 nf temperature ( c) 12.0 12.2 12.4 12.6 12.8 13.0 13.2 13.4 13.6 13.8 14.0 ? 40 ? 25 ? 105 203550658095110125 v drv(clmp_a) (v) @ v cc = 28 v and c load = 1 nf figure 14. driver clamp level ? a version, v cc = 28 v and c load = 1 nf temperature ( c) 12.5 13.0 13.5 14.0 14.5 15.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 v drv(clmp_a) (v) @ v cc = 28 v and c load = 10 nf figure 15. driver clamp level ? a version, v cc = 28 v and c load = 10 nf temperature ( c)
NCP4304A, ncp4304b http://onsemi.com 8 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 7.1 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 v drv(clmp_b) (v) @ v cc = 28 v and c load = 1 nf figure 16. driver clamp level ? b version, v cc = 28 v and c load = 1 nf temperature ( c) 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 v drv(clmp_b) (v) @ v cc = 28 v and c load = 10 nf figure 17. driver clamp level ? b version, v cc = 28 v and c load = 10 nf temperature ( c) 0.0 10.0 20.0 30.0 40.0 50.0 60.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 t pd_on (ns) figure 18. cs to drv turn ? on propagation delay temperature ( c) 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 t pd_off (ns) figure 19. cs to drv turn ? off propagation delay temperature ( c) 98.0 98.5 99.0 99.5 100.0 100.5 101.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 i shift_cs ( a) figure 20. cs pin shift current temperature ( c) ? 110.0 ? 100.0 ? 90.0 ? 80.0 ? 70.0 ? 60.0 ? 50.0 ? 40.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 v th_cs_on (mv) figure 21. cs turn ? on threshold temperature ( c)
NCP4304A, ncp4304b http://onsemi.com 9 1.96 1.98 2.00 2.02 2.04 2.06 2.08 2.10 2.12 ? 40 ? 25 ? 105 203550658095110125 v trig (v) figure 22. trigger input threshold voltage temperature ( c) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 ? 40 ? 25 ? 105 203550658095110125 figure 23. progagation delay from trigger input to drv turn ? off temperature ( c) t p_trig (ns) 99.0 99.5 100.0 100.5 101.0 101.5 ? 40 ? 25 ? 105 203550658095110125 trigl ight_load ( s) figure 24. light load transition timer duration temperature ( c) 9.175 9.180 9.185 9.190 9.195 9.200 9.205 9.210 ? 40 ? 25 ? 105 203550658095110125 trig ? light_load_rec ( s) figure 25. light load to normal operation recovery time temperature ( c) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 i trig ( a) figure 26. trigger input pulldown current temperature ( c) 156.0 157.0 158.0 159.0 160.0 161.0 162.0 163.0 164.0 165.0 ? 40 ? 25 ? 105 203550658095110125 t on_min (ns) @ r t_on_min = 0 figure 27. minimum on time @ r t_on_min = 0 temperature ( c)
NCP4304A, ncp4304b http://onsemi.com 10 994.0 994.5 995.0 995.5 996.0 996.5 997.0 997.5 998.0 998.5 999.0 ? 40 ? 25 ? 105 203550658095110125 t on_min (ns) @ r t_on_min = 10 figure 28. minimum on time @ r t_on_min = 10 temperature ( c) 991.0 991.5 992.0 992.5 993.0 993.5 994.0 994.5 ? 40 ? 25 ? 105 20355065809511012 5 figure 29. minimum off time @ r t_off_min = 10 temperature ( c) t off_min (ns) @ r t_off_min = 10 4680 4700 4720 4740 4760 4780 4800 4820 4840 4860 4880 ? 40 ? 25 ? 10 5203550658095110125 t off_min (ns) @ r t_off_min = 50 figure 30. minimum on time @ r t_on_min = 53 temperature ( c) 4760 4780 4800 4820 4840 4860 4880 4900 4920 4940 ? 40 ? 25 ? 105 20355065809511012 5 t on_min (ns) @ r t_on_min = 50 figure 31. minimum off time @ r t_off_min = 53 temperature ( c) 585.0 590.0 595.0 600.0 605.0 610.0 615.0 620.0 625.0 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 t off_min (ns) @ r t_off_min = 50 figure 32. minimum off time @ r t_off_min = 0 temperature ( c) 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 ? 40 ? 25 ? 105 20355065809511012 5 i cc1_a (ma) figure 33. internal ic consumption (a version, no load on pin 8, f sw = 500 khz, t on _ min = 500 ns, t off _ min = 620 ns) temperature ( c)
NCP4304A, ncp4304b http://onsemi.com 11 4.020 4.040 4.060 4.080 4.100 4.120 4.140 4.160 4.180 4.200 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 i cc1_b (ma) figure 34. internal ic consumption (b version, no load on pin 8, f sw = 500 khz, t on_min = 500 ns, t off_min = 620 ns) temperature ( c) 9.05 9.10 9.15 9.20 9.25 9.30 9.35 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 i cc2_a (ma) figure 35. internal ic consumption (a version, c load = 1 nf on pin 8, f sw = 400 khz, t on_min = 500 ns, t off_min = 620 ns) temperature ( c) 6.20 6.40 6.60 6.80 7.00 7.20 7.40 7.60 ? 40 ? 25 ? 105 203550658095110125 i cc2_b (ma) figure 36. internal ic consumption (b version, c load = 1 nf on pin 8, f sw = 400 khz, t on_min = 500 ns, t off_min = 620 ns) temperature ( c) 51.9 52.0 52.1 52.2 52.3 52.4 52.5 52.6 52.7 52.8 ? 40 ? 25 ? 105 203550658095110125 i cc3_a (ma) figure 37. internal ic consumption (a version, c load = 10 nf on pin 8, f sw = 400 khz, t on_min = 500 ns, t off_min = 620 ns) temperature ( c) 32.5 33.0 33.5 34.0 34.5 35.0 ? 40 ? 25 ? 105 203550658095110125 i cc3_b (ma) figure 38. internal ic consumption (b version, c load = 10 nf on pin 8, f sw = 400 khz, t on_min = 500 ns, t off_min = 620 ns) temperature ( c)
NCP4304A, ncp4304b http://onsemi.com 12 application information general description the NCP4304A/b is designed to operate either as a standalone ic or as a companion ic to a primary side controller to help achieve efficient synchronous rectification in switch mode power supplies. this controller features a high current gate driver along with high ? speed logic circuitry to provide appropriately timed drive signals to a synchronous rectification mosfet. with its novel architecture, the NCP4304A/b has enough versatility to keep the synchronous rectification efficient under any operating mode . the NCP4304A/b works from an available bias supply with voltage range from 10.4 v to 28 v (typical). the wide v cc range allows direct connection to the smps output voltage of most adapters such as notebook and lcd tv adapters. as a result, the NCP4304A/b simplifies circuit operation compared to other devices that require specific bias power supplies (e.g. 5 v). the high voltage capability of the v cc is also a unique feature designed to allow operation for a broader range of applications. precise turn off threshold of the current sense comparator together with accurate offset current source allows the user to adjust for any required turn off current threshold of the sr mosfet switch using a single resistor . compared to other sr controllers that provide turn off thresholds in the range of ? 10 mv to ? 5 mv, the NCP4304A/b offers a turn off threshold of 0 mv that in combination with a low r ds(on) sr mosfet significantly reduces the turn off current threshold and improves efficiency. to overcome issues after turn on and off events, the NCP4304A/b provides adjustable minimum on time and off time blanking periods. blanking times can be adjusted independently of ic v cc using resistors connected to gnd. if needed, blanking periods can be modulated using additional components. an ultrafast trigger input helps to implement synchronous rectification systems in ccm applications (like ccm flyback or forward). the time delay from trigger input to driver turn off event is 10 ns (typicaly). additionally, the trigger input can be used to disable the ic and activate a low consumption standby mode. this feature can be used to decrease standby consumption of an smps. finally , the NCP4304A/b features a special input that can be used to automatically compensate for sr mosfet parasitic inductance effect. this technique achieves the maximum available on ? time and thus optimizes efficiency when a mosfet in standard package (like to ? 220 or to247) is used. if a sr mosfet in smt package with negligible inductance is used, the compensation input is connected to gnd pin.
NCP4304A, ncp4304b http://onsemi.com 13 zero current detection and parasitic inductance compensation figure 39 shows the internal connection of the zcd circuitry on the current sense input. the synchronous rectification mosfet is depicted with it?s parasitic inductances to demonstrate operation of the compensation system. figure 39. zcd sensing circuitry functionality when the voltage on the secondary winding of the smps reverses , the body diode of m1 starts to conduct current and the voltage of m1?s drain drops approximately to ? 1 v. the cs pin sources current of 100 a that creates a voltage drop on the r shift_cs resistor. once the voltage on the cs pin is lower than v th_cs_on threshold, m1 is turned on. because of parasitic impedances, significant ringing can occur in the application. to overcome sudden turn ? off due to mentioned ringing , the minimum conduction time of the sr mosfet is activated. minimum conduction time can be adjusted using r _min_ton resistor. the sr mosfet is turned ? off as soon as the voltage on the cs pin is higher than v th_cs_off . for the same ringing reason, a minimum off time timer is asserted once the turn - off is detected. the minimum off time can be externally adjusted using r _min_toff resistor. mosfet m1 conducts when the secondary current decreases, therefore the turn ? off time depends on its r ds(on) . the 0 mv threshold provides an optimum switching period usage while keeping enough time margin for the gate turn off. the r shift_cs resistor provides the designer with the possibility to modify (increase) the actual turn - off current threshold .
NCP4304A, ncp4304b http://onsemi.com 14 figure 40. zcd comparators thresholds and blanking periods timing if no rshift_cs resistor is used, the turn ? on and turn ? off thresholds are fully given by the cs input specification (please refer to parametric table). once non ? zero r shift_cs resistor is used, both thresholds move down (i.e. higher mosfet turn off current) as the cs pin offset current causes a voltage drop that is equal to: v_rshift_cs rshift_cs * ishift_cs (eq. 1) final turn ? on and turn ? off thresholds can be then calculated as: vcs_turn_on vth_cs_on (rshift_cs * ishift_cs) (eq. 2) vcs_turn_off vth_cs_off (rshift_cs * ishift_cs) (eq. 3) note that r shift_cs impact on turn ? on threshold is less critical compar e to turn ? off threshold. if using a sr mosfet in to ? 220 package (or other package which features leads) , the parasitic inductance of the package leads causes a turn ? off current threshold increase. this is because current that flows through the sr mosfet has quite high di(t)/dt that induces error voltage on the sr mosfet leads inductance. this error voltage, that is proportional to the secondary current derivative, shifts the cs input voltage to zero when significant current still flows through the channel. zero current threshold is thus detected when current still flows through the sr mosfet channel ? please refer to figure 41 for better understanding. as a result, the sr mosfet is turned ? off prematurely and the efficiency of the smps is not optimized.
NCP4304A, ncp4304b http://onsemi.com 15 figure 41. waveforms from sr system using mosfet in to ? 220 package without parasitic inductance compensation ? sr mosfet channel conduction time is reduced note that the efficiency impact of the error caused by parasitic inductance increases with lower rds_on mosfets and/or higher operating frequency. the NCP4304A/b offers a way to compensate for mosfet parasitic inductances effect - refer to figure 42 . figure 42. package parasitic inductances compensation principle dedicated input (comp) offers the possibility to use an external compensation inductance (wire strap or pcb). if the value of this compensation inductance is l comp = l drain + l source , the compensation voltage created on this inductance is exactly the same as the sum of error voltages created on drain and source parasitic inductances i.e. vl drain + vl source . the internal analog inverter (figure 39) inverts compensation voltage vl_comp and offsets the current sense comparator turn ? off threshold. the current sense comparator thus ?sees? between its terminals a voltage that would be seen on the sr mosfet channel resistance in case the lead inductances wouldn?t exist. the current sense comparator of the NCP4304A/b is thus able to detect the secondary current zero crossing very precisely. more over, the secondary current turn ? off threshold is then di(t)/t independent thus the NCP4304A/b allows to increase operating frequency of the sr system. one should note that the parasitic resistance of compensation inductance should
NCP4304A, ncp4304b http://onsemi.com 16 be as low as possible compared to the sr mosfet channel and leads resistance otherwise compensation is not ef ficient. typical value of compensation inductance for a to ? 220 package is 7 nh. waveforms from the application with compensated sr system can be seen in figure 43. one can see the conduction time has been significantly increased and turn ? off current reduced. figure 43. waveforms sr system using mosfet in to ? 220 package with parasitic inductance compensation ? sr mosfet channel conduction time is optimized note that using the compensation system is only beneficial in applications that are using a low r ds(on) mosfet in non ? smt package. using the compensation method allows for optimized efficiency with a standard to220 package that in turn results in reduced costs, as the smt mosfets usually require reflow soldering process and more expensive pcb. from the above paragraphs and parameter tables it is evident that turn ? off threshold precision is quite critical. if we consider a sr mosfet with rds_on of 1 m , the 1 mv error voltage on the cs pin results in a 1 a turn ? off current threshold difference. thus the pcb layout is very critical when implementing the sr system. note that the cs turn ? off comparator as well as compensation inputs are referred to the gnd pin. any parasitic impedance (resistive or inductive ? talking about m and nh values) can cause a high error voltage that is then evaluated by the cs comparator. ideally the cs turn?off comparator should detect voltage that is caused by secondary current directly on the sr mosfet channel resistance. practically this is not possible because of the bonding wires, leads and soldering. to assure the best efficiency results, a kelvin connection of the sr controller to the power circuitry should be implemented (i.e. gnd pin should be connected to the sr mosfet source soldering point and current sense pin should be connected to the sr mosfet drain soldering point). any impact of pcb parasitic elements on the sr controller functionality is then avoided. figures 44 and 45 show examples of sr system layouts using parasitic inductance compensation (i.e. for low r ds(on) mosfet in to ? 220 package ) and not using compensation (i.e. for higher r ds(on) mosfet in to ? 220 package or smt package mosfets) .
NCP4304A, ncp4304b http://onsemi.com 17 figure 44. recommended layout when parasitic inductance compensation is used figure 45. recommended layout when parasitic inductance compensation is not used ncp4304 trigger/disable input the NCP4304A/b features an ultrafast trigger input that exhibits a typically of 1 0 ns delay from its activation to the turn ? off of the sr mosfet. the main purpose of this input is to turn - off the sr mosfet in applications operating in ccm mode via a signal coming from the primary side or direct synchronization sr mosfet turn ? on and turn ? off event according to primary controller signals . the NCP4304A/b operation can be disabled using the trigger/dis input. if the trigger/dis input is pulled high (above 2.5 v) the driver is disabled immediately , except during drv rising edge when trigger/dis is blanked for 150 ns. if the trigger signal is high for more than 100 s the driver enters standby mode. the ic consumption is reduced below 100 a during the standby mode. the device recovers operation in 10 s when the trigger voltage is increased to exit standby mode. trigger/dis input is superior to cs input except blanking period . trigger/dis signal turns ? off the sr mosfet or disable its turn ? on if trigger/dis is pulled above v trig . figure 46. trigger input internal circuitry trigger/dis figure 47 depicts driver turn ? on events. turn ? on of the sr mosfet is possible if cs (vds) signal falls under v th_cs_on threshold and trigger/dis is pulled low (t1 to t3 time interval). when the cs (vds) reached the v th_cs_on threshold and trigger/dis is pulled high the driver stays low (t6, t7 time markers) if the trigger/dis is high. if the trigger/dis is pulled low and cs (vds) is still under v th_cs_on threshold then the drv is turned ? on (t7 marker). time markers t14 and t15 in figure 47 demonstrate situation when cs (vds) is above v th_cs_on threshold and trigger/dis is pulled down. in this case the driver stays low (t12 to t15 marker).
NCP4304A, ncp4304b http://onsemi.com 18 figure 47. drv turn on events trig/dis the trigger/dis input is blanked for 150 ns after drv set signal to avoid undesirable behavior during sr mosfet turn ? on event. the blanking time in combination with high threshold voltage (2 v) prevent triggering on ringing and spikes that are present on the trigger/dis input pin during the sr mosfet turn ? on process. drv response to the short needle pulse on the trigger/dis pin is depicted in figure 48 ? this short pulse turns ? on the drv for 150 ns. figure 48. trigger needle pulse and trigger blank sequence trig/dis advantage of the trigger blanking time during drv turn ? on event is evident from figure 49. rising edge of the drv signal may cause additional spikes on the trigger/dis input. these spikes, in combination with ultra ? fast performance of the trigger logic , could turn ? off the sr mosfet in inappropriate time . implementation of the trigger blanking time period helps to avoid such situation .
NCP4304A, ncp4304b http://onsemi.com 19 figure 49. trigger blanking masked ? out noise in trigger signal during switch ? on event trig/dis figure 50 depicts driver turn ? off events in details. if the cs (v ds ) stays below v th_cs_off threshold driver is turned ? off according to rising edge of the trigger/dis signal. trigger/dis can turn ? off the driver also during minimum ? on time period (time marker t2 and t3 in figure 50). figure 51 depicts another driver turn ? off events in details. driver is turned ? off according to the cs (v ds ) signal (t2 marker) and only after minimum ? on time elapsed. trigger/dis signal needs to be low during this event. if the cs (v ds ) voltage reaches vth_cs_off threshold before minimum ? on time period ends and trigger/dis pin is low the drv is turned ? off on the falling edge of the minimum ? on time period (t4 and t6 time markers in figure 51). figure 52 depicts performance of the NCP4304A/b controller when trigger pin is permanently pulled low. in this case the drv is turned on and off according to the cs (v ds ) signal. the driver can be turned off only after minimum ? on time period elapsed. the driver is turned ? on in the time when cs (vds) reaches v th_cs_on threshold (t1 ? t2, t5 ? t6, t9 ? t10 markers). drv is turned ? off if cs (v ds ) signal reaches v th_cs_off threshold (t4 marker). the drv on ? time is prolonged till minimum ? on time period falling edge if the cs (vds) reaches v th_cs_off before minimum ? on time period elapsed (t7 ? t8, t11 ? t12 markers). figure 53 depicts entering into the sleep mode. if the trigger/dis is pulled up for more than 100 s the NCP4304A/b enters low consumption mode. the drv stays low (disabled) during entering sleep mode. figure 54 shows sleep mode transition 2nd case ? i.e. trigger rising edge comes during the trigger blank period. figure 55 depicts entering into sleep mode and wake ? up sequence. figures 56 and 57 show wake ? up situations in details. if the NCP4304A/b is in sleep mode and t rigger/dis is pulled low NCP4304A/b requires up to 10 s period to recover all internal circuitry to normal operation mode. the driver is then enabled in the next cycle of cs (vds) signal only. the drv stays low during waking ? up time period.
NCP4304A, ncp4304b http://onsemi.com 20 figure 50. driver turn ? off events based on the trigger input trig/dis figure 51. driver off sequence chart 2 trig/dis
NCP4304A, ncp4304b http://onsemi.com 21 figure 52. trigger/dis is low sequence chart trig/dis figure 53. trigger/dis from low to high sequence 1 trig/dis
NCP4304A, ncp4304b http://onsemi.com 22 figure 54. trigger/dis from low to high sequence 2 trig/dis figure 55. sleep mode sequence trig/dis
NCP4304A, ncp4304b http://onsemi.com 23 figure 56. waking ? up sequence trig/dis figure 57. wake ? up time sequence trig/dis figure 58 shows ic behavior in case the trigger signal features two pulses during one cycle of the v ds (cs) signal. trigger enables driver at time t1 and drv turns on because the v ds voltage is under v th_cs_on threshold voltage. the trigger signal and consequently drv output fall down in time t2. the minimum off time generator is triggered in time t2. trigger drops down to low level in time t3 but there is still minimum off time sequence present so the drv output stays low. when the minimum off time sequence elapses in time t4 the drv is turned on. in time t5 trigger signal rises up and terminates this cycle of the cs signal in time t5. next cycle starts in time t6. t rigger enables drv and v ds is under v th_cs_on threshold voltage so drv turns on in time t6. t rigger signal rises up to high level in time t7, consequently drv turns off and this starts minimum off time generator. because minimum off time period is longer then the rest of time to the end of cycle of v ds ? drv is disabled.
NCP4304A, ncp4304b http://onsemi.com 24 figure 58. ic behavior when multiple trigger pulses appear on trigger input trig/dis note that the trigger input is an ultrafast input that is sensitive even to very narrow voltage pulses . thus it is wise to keep this input on a low impedance path and provide it with a clean triggering signal in the time this input is enabled by internal logic. a typical application schematic of a ccm flyback converter with the NCP4304A/b driver can be seen in figure 59. in this application the trigger signal is taken directly from the flyback controller driver output and transmitted to the secondary side by pulse transformer tr2. because the trigger input is edge sensitive, it is not necessary to transmit the entire primary driver pulse to the secondary. the coupling capacitor c5 is used to allow pulse transformer core reset and also to prepare a needle pulse (a pulse with width lower than 100 ns) to be transmitted to the NCP4304A/b trigger input. the advantage of needle trigger pulse usage is that the required volt ? second product of the pulse transformer is very low and that allows the designer to use very small and cheap magnetics. the trigger transformer can be for instance prepared on a small toroidal ferrite core with diameter of 8 mm. proper safety insulation between primary and secondary sides can be easily assured by using triple insulated wire for one or even both windings. the primary mosfet gate voltage rising edge is delayed by external circuitry consisting of transistors q1, q2 and surrounding components. the primary mosfet is thus turned ? on with a slight delay so that the secondary controller turns ? off the sr mosfet by trigger signal prior to the primary switching. this method reduces the commutation losses and the sr mosfet drain voltage spike, which results in improved efficiency. it is also possible to use capacitive coupling (use additional capacitor with safety insulation) between the primary and secondary to transmit the trigger signal. we do not recommend this technique as the parasitic capacitive currents between primary and secondary may affect the trigger signal and thus overall system functionality.
NCP4304A, ncp4304b http://onsemi.com 25 figure 59. typical application schematic when NCP4304A/b is used in ccm flyback converter vbulk flyback control circuitry +vout gnd ok1 r1 r2 r3 r4 r5 r6 r7 r9 r10 c1 c2 c3 c4 c5 c6 c7 d2 d3 d4 d5 tr1 tr2 m1 m2 d1 q1 q2 r11 + + + vcc drv fb cs delay generator trig minimum t on and t off adjustment the NCP4304A/b offers adjustable minimum on and off time periods that ease the implementation of the synchronous rectification system in a power supply . these timers avoid false triggering on the cs input after the mosfet is turned on or off. the adjustment is based on an internal timing capacitance and external resistors connected to the gnd pin ? refer to figure 60 for better understanding. figure 60. internal circuitry of min ton_generator (min toff_generator works in the same way) current through the min_ton adjust resistor can be calculated as: i r_ton_min v ref r ton_min (eq. 4) as the same current is used for the internal timing capacitor (ct) charging, one can calculate the minimum on ? time duration using this equation. t on_min c t v ref i r_ton_min c t v ref v ref r ton_min (eq. 5) c t r ton_min as can be seen from equation 5, the minimum on and off times are independent of the vref or vcc level. the
NCP4304A, ncp4304b http://onsemi.com 26 internal capacitor size would be too high if we would use directly i r_ton_min current thus this current is decreased by the internal current mirror ratio. one can then calculate the minimum t on and t off blanking periods using below equations: t on_min 9.82 * 10 ? 11 *r t_on_min 4.66 * 10 ? 8 [ s] (eq. 6) t off_min 9.56 * 10 ? 11 *r t_off_min 5.397 * 10 ? 8 [ s] (eq. 7) note that the internal timing comparator delay affects the accuracy of equations equations 6 and 7 when minimum t on /t off times are selected near to their minimum possible values. please refer to figure 61 and 62 for measured minimum on and off time charts. figure 61. min_ton adjust characteristic figure 62. min_toff adjust characteristic 0 1 2 3 4 5 6 0 102030405060 r min_ton (k ) t on_min ( s) 0 1 2 3 4 5 6 0 102030405060 r min_toff (k ) t off_min ( s) the absolute minimum t on duration is internally clamped to 300 ns and minimum t off duration to 600 ns in order to prevent any potential issues with the minimum ton and/or t off input being shorted to gnd. some applications may require adaptive minimum on and off time blanking periods. with NCP4304A/b it is possible to modulate blanking periods by using an external npn transistor ? refer to figure 63. the modulation signal can be derived based on the load current or feedback regulator voltage. figure 63. possible connection for min t_on and min t_off modulation in llc applications with a very wide operating frequency range it is necessary to have very short minimum on time and off time periods in order to reach the required maximum operating frequency. however, when a llc converter operates under low frequency, the minimum off time period may then be too short. to overcome possible issues with the llc operating under low line and light load conditions, one can prolong the minimum off time blanking period by using resistors r drain1 and r drain2 connected from the opposite sr mosfet drain ? refer to figure 64 .
NCP4304A, ncp4304b http://onsemi.com 27 figure 64. possible connection for min toff prolongation in llc application with wide operating frequency range trig/dis trig/dis note that r drain1 and r drain2 should be designed in such a way that the maximum pulse current into the min_toff adjust pin is below 10 ma. voltage on the min toff and ton pins is clamped by internal zener protection to 10 v. power dissipation calculation it is important to consider the power dissipation in the mosfet driver of a sr system. if no external gate resistor is used and the internal gate resistance of the mosfet is very low, nearly all energy losses related to gate charge are dissipated in the driver. thus it is necessary to check the sr driver power losses in the target application to avoid over temperature and to optimize efficiency. in sr systems the body diode of the sr mosfet starts conducting before turn on because the v th_cs_on threshold level is below 0 v. on the other hand , the sr mosfet turn off process always starts before the drain to source voltage rises up significantly. therefore, the mosfet switch always operates under zero voltage switching (zvs) conditions when implemented in a synchronous rectification system. the following steps show how to approximately calculate the power dissipation and die temperature of the NCP4304A/b controller. note that real results can vary due to the effects of the pcb layout on the thermal resistance. step 1 ? mosfet gate ? to ? source capacitance: during zvs operation the gate to drain capacitance does not have a miller effect like in hard switching systems because the drain to source voltage is close to zero and its change is negligible.
NCP4304A, ncp4304b http://onsemi.com 28 c iss c gs c gd c rss c gd c oss c ds c gd figure 65. typical mosfet capacitance dependency on v ds and v gs voltage therefore, the input capacitance of a mosfet operating in zvs mode is given by the parallel combination of the gate to source and gate to drain capacitances (i.e. c iss capacitance for given gate to source voltage). the total gate charge , q g_total , of most mosfets on the market is defined for hard switching conditions. in order to accurately calculate the driving losses in a sr system, it is necessary to determine the gate charge of the mosfet for operation specifically in a zvs system. some manufacturers define this parameter as q g_zvs . unfortunately , most datasheets do not provide this data. if the c iss (or q g_zvs ) parameter is not available then it will need to be measured. please note that the input capacitance is not linear (as shown figure 65) and it needs to be characterized for a given gate voltage clamp level. step 2 ? gate drive losses calculation: gate drive losses are affected by the gate driver clamp voltage. gate driver clamp voltage selection depends on the type of mosfet used (threshold voltage versus channel resistance). the total power losses (driving loses and conduction losses) should be considered when selecting the gate driver clamp voltage. most of today?s mosfets for sr systems feature low r ds(on) for 5 v v gs voltage and thus it is beneficial to use the b version. however, there is still a big group of mosfets on the market that require higher gate to source voltage ? in this case the a version should be used. the total driving loss can be calculated using the selected gate driver clamp voltage and the input capacitance of the mosfet: p drv_total v cc v clamp c g_zvs f sw (eq. 8) where: v cc is the supply voltage v clamp is the driver clamp voltage c g_zvs is the gate to source capacitance of the mosfet in zvs mode f sw is the switching frequency of the target application the total driving power loss won?t only be dissipated in the ic , but also in external resistances like the external gate resistor (if used) and the mosfet internal gate resistance (figure 66). because NCP4304A/b features a clamped driver, it?s high side portion can be modeled as a regular driver switch with equivalent resistance and a series voltage source. the low side driver switch resistance does not drop immediately at turn ? off, thus it is necessary to use an equivalent value (r drv_low_eq ) for calculations. this method simplifies power losses calculations and still provides acceptable accuracy. internal driver power dissipation can then be calculated using equation 9: figure 66. equivalent schematic of gate drive circuitry
NCP4304A, ncp4304b http://onsemi.com 29 p drv_ic 1 2 c g_zvs v clamp 2 f sw r drv_low_eq r drv_low_eq r g_ext r g_int c g_zvs v clamp f sw v cc v clamp (eq. 9) 1 2 c g_zvs v clamp 2 f sw r drv_high_eq r drv_high_eq r g_ext r g_int where: r drv_low_eq is the ddriver low side switch equivalent resistance (1.55 ) r drv_high_eq is the driver high ? side switch equivalent resistance (7 ) r g_ext is the external gate resistor (if used) r g_int is the internal gate resistance of the mosfet step 3 ? ic consumption calculation: in this step, power dissipation related to the internal ic consumption is calculated. this power loss is given by the i cc current and the ic supply voltage. the i cc current depends on switching frequency and also on the selected min ton and toff periods because there is current flowing out from the min ton and toff pins. the most accurate method for calculating these losses is to measure the i cc current when c load = 0 nf and the ic is switching at the target frequency with given min_ton and min_toff adjust resistors. refer also to figure 67 for typical ic consumption charts when the driver is not loaded. ic consumption losses can be calculated as: p icc v cc i cc (eq. 10) step 4 ? ic die temperature arise calculation: the die temperature can be calculated now that the total internal power losses have been determined (driver losses plus internal ic consumption losses). the so ? 8 package thermal resistance is specified in the maximum ratings table for a 35 m thin copper layer with no extra copper plates on any pin (i.e. just 0.5 mm trace to each pin with standard soldering points are used). the die temperature is calculated as: t die p drv_ic p icc r j a t a (eq. 11) where: p drv_ic is the ic driver internal power dissipation p icc is the ic control internal power dissipation r ja is the thermal resistance from junction to ambient t a is the ambient temperature 0 20 40 60 80 100 120 140 160 180 50 100 150 200 250 300 350 400 450 500 operating frequency (khz) power consumtion (mw) b version, v cc = 12 v b version, v cc = 30 v a version, v cc = 12 v a version, v cc = 30 v figure 67. ic power consumption as a function of frequency for c load = 0 nf, r ton min = r toff min = 5 k 0 50 100 150 200 250 300 350 400 50 100 150 200 250 300 350 400 450 50 0 power consumtion (mw) operating frequency (khz) b version, v cc = 30 v b version, v cc = 12 v a version, v cc = 12 v a version, v cc = 30 v figure 68. ic power consumption as a function of frequency for c load = 1 nf, r ton min = r toff min = 5 k
NCP4304A, ncp4304b http://onsemi.com 30 0 100 200 300 400 500 600 700 800 50 100 150 200 250 300 350 400 450 500 power consumtion (mw) operating frequency (khz) b version, v cc = 30 v b version, v cc = 12 v a version, v cc = 12 v a version, v cc = 30 v figure 69. ic power consumption as a function of frequency for c load = 10 nf, r ton_min = r toff_min = 5 k
NCP4304A, ncp4304b http://onsemi.com 31 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
NCP4304A, ncp4304b http://onsemi.com 32 package dimensions dfn8 4x4 case 488af ? 01 issue c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 4.00 bsc d2 1.91 2.21 e 4.00 bsc e2 2.09 2.39 e 0.80 bsc k 0.20 ??? l 0.30 0.50 d b e c 0.15 a c 0.15 2x 2x top view side view bottom view ?? ? ? ? ? ? ? c 0.08 c 0.10 ?? ? ? ? ?? e 8x l k e2 d2 b note 3 1 4 5 8 8x 0.10 c 0.05 c ab pin one reference *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 8x 0.63 2.21 2.39 8x 0.80 pitch 4.30 0.35 l1 detail a l optional constructions ??? ?? ?? ??? 0.15 detail b note 4 detail a dimensions: millimeters package outline on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp4304/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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